Chip startup XCENA raises $135M to tackle AI’s memory bottleneck

Every time you ask ChatGPT a question, your request triggers a complex data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy computation, and then makes its way back—a journey that repeats for every single word the AI generates. This structural bottleneck requires routing through the industry’s most expensive and power-intensive chips, creating massive inefficiencies that the startup XCENA aims to eliminate.

The four-year-old company, with offices in South Korea and the U.S., has designed a chip that places compute capabilities much closer to DRAM. By allowing routine data operations to be handled near memory, the technology avoids costly round trips between processors. This memory-centric architecture has attracted significant investment, with XCENA recently raising $135 million in a Series B at a $570 million valuation, bringing its total funding to $185 million.

XCENA’s chip, known as the MX1, connects to the CPU through CXL (Compute Express Link), creating a dedicated express lane for data. The company claims that tasks which previously required ten servers could potentially run on just one by bringing compute to the data. While GPUs handle the heavy math of AI training, the MX1 manages data orchestration, including preprocessing and KV cache management, directly within the memory module itself.

CEO Jin Kim co-founded the company in 2022 alongside veterans from Samsung and SK Hynix, the giants currently dominating the global memory market. Kim notes that while processors have become smarter over decades, memory has lagged behind, making inference a memory scaling problem rather than just a compute one. This shift is timely, as the major memory vendors have recently crossed trillion-dollar valuations amid surging demand for more efficient infrastructure.

The company differentiates itself from rivals like Marvell and Astera Labs through deep vertical integration. Using thousands of efficient RISC-V cores, XCENA designs its own internal memory hierarchy and DRAM controller rather than outsourcing these components. While the MX1 is currently a prototype, mass production is scheduled for 2026 at Samsung’s foundry, with the company targeting hyperscalers looking to save hundreds of millions in long-term infrastructure costs.

XCENA’s innovation addresses the core inefficiency of modern AI by rethinking how data moves between memory and processors. As the industry shifts toward memory-centric computing, the startup’s ability to reduce power consumption and hardware footprints could redefine the economics of large-scale AI deployments. To stay informed on the latest developments in semiconductor technology and venture capital, subscribe to our newsletter for exclusive industry insights.

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